中文名: 數字信號開發
英文名: Altera Quartus II DSP Builder
資源格式: 光盤鏡像
版本: V9.1 incl SP2 Linux
發行時間: 2010年
制作發行: Altera Corporation
地區: 美國
語言: 英文
簡介:

官方站點 http://www.altera.com/products/software/qu...dex.html
利用DSP Builder技術，您在幾分鐘內就可以使用業界標准The MathWorks/Simulink工具完成系統定義/仿真，直至系統實現。
DSP Builder信號編譯器模塊讀取由DSP Builder和MegaCore®模塊構建的Simulink模型文件(.mdl)，生成VHDL文件和工具命令語言(Tcl)腳本，進行綜合，實現硬件，並完成仿真。
Altera與The Mathworks密切協作，確保您獲得Altera® FPGA的性價比優勢，同時能夠使用Simulink——The MathWorks基於模型設計的業界最佳工具。
Altera的Simulink至FPGA綜合技術在業界獨具特色，它現在支持Simulink設計表征時序驅動綜合。利用該技術，您第一次能夠自動生成基於高級Simulink設計描述的時序最佳寄存器傳送級(RTL)代碼。使用這一新的DSP Builder功能，您在幾分鐘內就可以實現高性能設計，達到峰值FPGA性能。相對於手動優化HDL代碼需要的數小時甚至幾天時間相比，這大大提高了效能。

What's new in Quartus II design software version 9.1?
Quartus® II software version 9.1 delivers the #1 performance and productivity for FPGA, CPLD, and HardCopy® ASIC designs. This new release supports Altera's new lowest cost, lowest power FPGA family—Cyclone® IV GX FPGAs with integrated 3.125-Gbps transceivers. The Cyclone IV GX FPGA family is targeted to high-volume, cost-sensitive applications, enabling you to meet increasing bandwidth requirements while lowering costs. Version 9.1 further extends Quartus II software's productivity advantage by delivering 20 percent overall compile time reduction over Quartus II software version 9.0, and maintains 2x to 3x faster compile times than the nearest competitor for high-density 65-nm and 40-nm designs. In addition, the new Rapid Recompile feature in version 9.1 reduces compile times by 50 percent (on average) compared to a full compile when small engineering change order (ECO)-type design changes are made. Finally, this release also supports the largest FPGA in the industry—Stratix® IV E EP4SE820 devices.

New Rapid Recompile for Faster Design Iteration
The new Rapid Recompile feature enhances Quartus II software's ability to further minimize design compilation times. Rapid Recompile maximizes productivity by enabling faster small ECO-type design changes after a full compile, reducing compilation times by 50 percent (on average) versus running another full compile on the design. Rapid Recompile also significantly improves productivity during timing closure by preserving critical timing during late design changes.

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